1. Field of the Invention
The present invention relates to a synchronizer, and more particularly, to a synchronizer for use in a semiconductor integrated circuit having a plurality of power supply regions which include a power supply region in which a power supply voltage changes.
2. Description of the Related Art
Clocking is a very important technique for designing a high speed digital system. This is because, in a CPU, a clock frequency determines a data processing speed, and in an I/O bus or a memory bus, a clock frequency determines a data transfer speed.
One of the problems which must be solved to speed up a clock frequency is a clock skew.
As a clock distribution system for reducing a clock skew, there is known an H-clock tree for configuring a clock distribution network by using a combination of wiring blocks. However, it is impossible to completely eliminate a clock skew.
Therefore, a problem with a clock skew is solved by using a synchronizer such as a PLL (Phase-locked loop) circuit, and a high speed digital system is implemented.
FIG. 1 shows a synchronizer using a PLL.
With respect to a clock distribution network, all of the wiring lengths from an output terminal of the PLL circuit PLL to a plurality of terminals (such as nA, nB, for example) are equal to each other, and in a plurality of paths, a design is made so that a delay of a clock signal caused by a wiring resistance or a wiring capacity is equal to another delay.
An input/output buffer I/O operates in synchronism with a clock signal CLK (=nP1). On the other hand, an internal circuit connected to one of the plurality of terminals (end points) of the clock distribution network operates in synchronism with, for example, a clock signal CLK (=nPIA=nA=nB).
Here, the clock signal CLK (0 nPIA=nA=nB) is delayed in predetermined quantity relevant to the clock signal CLK (=nPI) due to an effect such as the wiring resistance or wiring capacity caused by the clock distribution network.
The PLL circuit PLI is used to eliminate a phase shift caused by this delay and to obtain synchronization between the clock signal CLK (=nPIA=nA=nB)and the clock signal CLK (=nPI) (refer to Jpn. Pat. Appln. KOKAI Publication Nos. 2000-347764, 9-326689, and 8-321773, and I. A. Young: “A PLL clock generator with 5 to 110 MHz of lock range for microprocessors”, IEEE J. Solid-State Circuit, Volume 27, Issue 11, November 1992).
In the case where a semiconductor integrated circuit 11 operates at a single power supply voltage, an internal clock signal and an external clock signal are synchronized with each other by using such a synchronizer, thereby making it possible to carry out normal operation.
As shown in an example of FIG. 1, however, in the case where the semiconductor integrated circuit 11 has a plurality of power supply regions and one of them is a power supply region in which a power supply voltage changes, a problem occurs.
For example, when the power supply voltages of the power supply regions A and B are always equal to each other, the phase of the clock signal CLK (=nPIA=nA=nB) and the phase of the clock signal (=nPI) coincide with each other.
However, assuming that the power supply voltage in the power supply region B drops, the delay quantity of the clock signal in the power supply region B becomes greater than that of the clock signal in the power supply region A. Therefore, the phase of the clock signal CLK (=nB) and the phase of the clock signal CLK (=nPI=nPIA=nA) are shifted from each other.
If the phases of the clock signals LK between the plurality of power supply regions A and B are thus shifted from each other, finally, this phase shift causes a malfunction of a whole system which includes the semiconductor integrated circuit 11.
There exists a technique for connecting power supply regions A and B each other by means of a buffer memory and eliminating a phase shift between the power supply regions A and B by using this buffer memory.
In this case, however, a general synchronizer circuit design technique becomes unavailable, and there occur problems with a complicated circuit operation, an increased circuit area, a degraded performance (increased latency), an increased development cost, and the like.